142 search results - page 7 / 29 » Functional test generation for non-scan sequential circuits |
ITC
1989
IEEE
15 years 1 months ago
1989
IEEE
: The concept of a pseudo-exhaustive test for sequential circuits is introduced in a similar way as it is used for combinational networks. Instead of test sets one has to apply pse...
ICCAD
1994
IEEE
15 years 1 months ago
1994
IEEE
This paper presents a new method of selecting scan
ipops (FFs) in partial scan designs of sequential circuits. Scan FFs are chosen so that the whole circuit can be partitioned in...
ICCAD
1996
IEEE
15 years 1 months ago
1996
IEEE
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...
ICTAI
2002
IEEE
15 years 2 months ago
2002
IEEE
In order to reduce the time-to-market and simplify gatelevel test generation for digital integrated circuits, GAbased functional test generation techniques are proposed for behavi...
ICCAD
2000
IEEE
15 years 2 months ago
2000
IEEE
A method to select the lengths of functional sequences in a BIST scheme for scan designs is proposed in this paper. A functional sequence is a sequence of primary input vectors ap...