115 search results - page 7 / 23 » Fusion of Loops for Parallelism and Locality |
107
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IPPS
2010
IEEE
14 years 9 months ago
2010
IEEE
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...
111
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CASES
2009
ACM
15 years 6 months ago
2009
ACM
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
138
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ASPLOS
1994
ACM
15 years 3 months ago
1994
ACM
In the past decade, processor speed has become significantly faster than memory speed. Small, fast cache memories are designed to overcome this discrepancy, but they are only effe...
99
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ICPP
1996
IEEE
15 years 3 months ago
1996
IEEE
Tiling exploits temporal reuse carried by an outer loop of a loop nest to enhance cache locality. Loop skewing is typically required to make tiling legal. This restricts parallelis...
SAC
2002
ACM
14 years 11 months ago
2002
ACM
This paper presents a novel approach for the problem of generating tiled code for nested for-loops using a tiling transformation. Tiling or supernode transformation has been widel...