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ICPP
2008
IEEE
16 years 21 days ago
Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches
This paper presents a two-part study on managing distributed NUCA (Non-Uniform Cache Architecture) L2 caches in a future manycore processor to obtain high singlethread program per...
Lei Jin, Sangyeun Cho
146
Voted
IPPS
2008
IEEE
16 years 20 days ago
Massive supercomputing coping with heterogeneity of modern accelerators
Heterogeneous supercomputers with combined general purpose and accelerated CPUs promise to be the future major architecture due to their wideranging generality and superior perfor...
Toshio Endo, Satoshi Matsuoka
IROS
2008
IEEE
108views Robotics» more  IROS 2008»
16 years 20 days ago
Intercontinental multimodal tele-cooperation using a humanoid robot
— In multimodal tele-cooperation as considered in this paper two humans in distant locations jointly perform a task requiring multimodal including haptic feedback. One human oper...
Angelika Peer, Sandra Hirche, Carolina Weber, Inga...
ISCA
2008
IEEE
205views Hardware» more  ISCA 2008»
16 years 20 days ago
VEAL: Virtualized Execution Accelerator for Loops
Performance improvement solely through transistor scaling is becoming more and more difficult, thus it is increasingly common to see domain specific accelerators used in conjunc...
Nathan Clark, Amir Hormati, Scott A. Mahlke
ISVLSI
2008
IEEE
118views VLSI» more  ISVLSI 2008»
16 years 20 days ago
MPI-Based Adaptive Task Migration Support on the HS-Scale System
Scalability of architecture, programming model and task control management will be a major challenge for future VLSI systems. In this context, homogeneous MPSOC is a seducing appr...
Nicolas Saint-Jean, Pascal Benoit, Gilles Sassatel...