2291 search results - page 403 / 459 » Future Graphics Architectures |
MOBIHOC
2009
ACM
16 years 13 days ago
2009
ACM
Most future large-scale sensor networks are expected to follow a two-tier architecture which consists of resource-rich master nodes at the upper tier and resource-poor sensor node...
115
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VLSID
2004
IEEE
16 years 8 days ago
2004
IEEE
As chip complexity grows, design productivity boost is expected from reuse of large parts and blocks of previous designs with the design effort largely invested into the new parts...
HPCA
2008
IEEE
16 years 7 days ago
2008
IEEE
Increases in peak current draw and reductions in the operating voltages of processors continue to amplify the importance of dealing with voltage fluctuations in processors. Noise-...
EUROSYS
2010
ACM
15 years 9 months ago
2010
ACM
Symmetric-ISA (instruction set architecture) asymmetricperformance multicore processors were shown to deliver higher performance per watt and area for codes with diverse architect...
128
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VEE
2010
ACM
15 years 6 months ago
2010
ACM
Asymmetric multicore processors (AMP) consist of cores exposing the same instruction-set architecture (ISA) but varying in size, frequency, power consumption and performance. AMPs...