13 search results - page 2 / 3 » GPE: A New Representation for VLSI Floorplan Problem |
ASPDAC
2000
ACM
13 years 10 months ago
2000
ACM
Simulated annealing has been one of the most popular stochastic optimization methods used in the VLSI CAD field in the past two decades for handling NP-hard optimization problems...
ICCD
2001
IEEE
14 years 3 months ago
2001
IEEE
Classical floorplanning minimizes a linear combination of area and wirelength. When Simulated Annealing is used, e.g., with the Sequence Pair representation, the typical choice o...
ICCAD
1994
IEEE
13 years 10 months ago
1994
IEEE
In this paper, we study the area-balanced multi-way partitioning problem of VLSI circuits based on a new dual netlist representation named the hybrid dual netlist (HDN), and propo...
TCAD
2002
13 years 5 months ago
2002
This paper describes an application of a Constructive Genetic Algorithm (CGA) to the Gate Matrix Layout Problem (GMLP). The GMLP happens in very large scale integration (VLSI) desi...
SLIP
2005
ACM
13 years 11 months ago
2005
ACM
Routability optimization has become a major concern in the physical design cycle of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominan...