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» GPE: A New Representation for VLSI Floorplan Problem
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ASPDAC
2000
ACM
154views Hardware» more  ASPDAC 2000»
13 years 10 months ago
Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application
Simulated annealing has been one of the most popular stochastic optimization methods used in the VLSI CAD field in the past two decades for handling NP-hard optimization problems...
Jason Cong, Tianming Kong, Faming Liang, Jun S. Li...
ICCD
2001
IEEE
103views Hardware» more  ICCD 2001»
14 years 3 months ago
Fixed-outline Floorplanning through Better Local Search
Classical floorplanning minimizes a linear combination of area and wirelength. When Simulated Annealing is used, e.g., with the Sequence Pair representation, the typical choice o...
Saurabh N. Adya, Igor L. Markov
ICCAD
1994
IEEE
151views Hardware» more  ICCAD 1994»
13 years 10 months ago
Multi-way VLSI circuit partitioning based on dual net representation
In this paper, we study the area-balanced multi-way partitioning problem of VLSI circuits based on a new dual netlist representation named the hybrid dual netlist (HDN), and propo...
Jason Cong, Wilburt Labio, Narayanan Shivakumar
TCAD
2002
110views more  TCAD 2002»
13 years 5 months ago
A constructive genetic algorithm for gate matrix layout problems
This paper describes an application of a Constructive Genetic Algorithm (CGA) to the Gate Matrix Layout Problem (GMLP). The GMLP happens in very large scale integration (VLSI) desi...
Alexandre César Muniz de Oliveira, Luiz Ant...
SLIP
2005
ACM
13 years 11 months ago
Congestion prediction in early stages
Routability optimization has become a major concern in the physical design cycle of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominan...
Chiu-Wing Sham, Evangeline F. Y. Young