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GRAPHITE
2005
ACM
15 years 3 months ago
Sketching with a low-latency electronic ink drawing tablet
Drawing on paper is an experience which is still unmatched by any input device for drawing into a computer in terms of accuracy, dexterity and general pleasantness of use. This pa...
Alex Henzen, Neculai Ailenei, Fabian Di Fiore, Fra...
VTS
2005
IEEE
95views Hardware» more  VTS 2005»
15 years 3 months ago
SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms
Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typ...
Baosheng Wang, Yuejian Wu, Josh Yang, André...
VTS
1998
IEEE
98views Hardware» more  VTS 1998»
15 years 2 months ago
Experimental Results for IDDQ and VLV Testing
An experimental test chip was designed and manufactured to evaluate different test techniques. Based on the results presented in the wafer probe, 309 out of 5491 dies that passed ...
Jonathan T.-Y. Chang, Chao-Wen Tseng, Yi-Chin Chu,...
JFR
2007
103views more  JFR 2007»
14 years 9 months ago
Evolving interface design for robot search tasks
This paper describes two steps in the evolution of human-robot interaction designs developed by the University of Massachusetts Lowell (UML) and the Idaho National Laboratory (INL...
Holly A. Yanco, Brenden Keyes, Jill L. Drury, Curt...
JSSPP
1997
Springer
15 years 1 months ago
An Experimental Evaluation of Processor Pool-Based Scheduling for Shared-Memory NUMA Multiprocessors
In this paper we describe the design, implementation and experimental evaluation of a technique for operating system schedulers called processor pool-based scheduling [51]. Our tec...
Tim Brecht