44 search results - page 3 / 9 » Gate delay calculation considering the crosstalk capacitance... |
DAC
2003
ACM
13 years 11 months ago
2003
ACM
In recent years, due to rapid advances in VLSI manufacturing technology capable of packing more and more devices and wires on a chip, crosstalk has emerged as a serious problem af...
ISLPED
2007
ACM
13 years 7 months ago
2007
ACM
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors ...
VLSID
1999
IEEE
13 years 10 months ago
1999
IEEE
We describe an improved iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. The speed and accuracy of our approach mak...
ICCAD
2003
IEEE
14 years 3 months ago
2003
IEEE
This paper proposes a scheme that captures diverse input waveforms of CMOS gates for static timing analysis. Conventionally the latest arrival time and transition time are calcula...
GLVLSI
2003
IEEE
13 years 11 months ago
2003
IEEE
—Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effectiv...