44 search results - page 8 / 9 » Gate delay calculation considering the crosstalk capacitance... |
ICCAD
1994
IEEE
13 years 10 months ago
1994
IEEE
In this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrou...
ICCD
2004
IEEE
14 years 3 months ago
2004
IEEE
In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the correct functionality and largely impact the performance of complex System-on-Chip (SoC) designs. F...
DAC
2004
ACM
13 years 11 months ago
2004
ACM
Leakage current has become a stringent constraint in today’s processor designs in addition to traditional constraints on frequency. Since leakage current exhibits a strong inver...
GLVLSI
2006
IEEE
14 years 9 days ago
2006
IEEE
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...
ISPD
2005
ACM
13 years 12 months ago
2005
ACM
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...