14 search results - page 2 / 3 » Gate delay estimation in STA under dynamic power supply nois... |
ICCAD
2003
IEEE
13 years 11 months ago
2003
IEEE
The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has...
VTS
2002
IEEE
13 years 11 months ago
2002
IEEE
A device testing method called Transient Signal Analysis (TSA) is subjected to elements of a real process and testing environment in this paper. Simulations experiments are design...
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
—Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits is presented in this paper. Noise immunity is enhanced by conditionally turning on the conditional k...
ISLPED
2003
ACM
13 years 11 months ago
2003
ACM
We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous a...
TVLSI
2010
13 years 28 days ago
2010
Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise mar...