36 search results - page 6 / 8 » Gate sizing for large cell-based designs |
FPGA
2003
ACM
13 years 11 months ago
2003
ACM
In this paper, we present the first exact algorithm to solve the constrained I/O placement problem for FPGAs that support multiple I/O standards. We derive a compact integer line...
DATE
2007
IEEE
14 years 19 days ago
2007
IEEE
This paper presents a new blocking logic to block unknowns for temporal compactors. The proposed blocking logic can reduce data volume required to control the blocking logic and a...
ICCAD
2006
IEEE
14 years 3 months ago
2006
IEEE
This work describes a new mapping technique, RAM-MAP, that identifies parts of circuits that can be efficiently mapped into the synchronous embedded memories found on field prog...
TCAD
2010
13 years 1 months ago
2010
Design debugging is a major bottleneck in modern VLSI design flows as both the design size and the length of the error trace contribute to its inherent complexity. With typical des...
FPL
2010
Springer
13 years 4 months ago
2010
Springer
One of the more popular placement algorithms for Field Programmable Gate Arrays (FPGAs) is called Simulated Annealing (SA). This algorithm tries to create a good quality placement ...