24 search results - page 3 / 5 » Gated Clock Routing Minimizing the Switched Capacitance |
ISLPED
2003
ACM
15 years 2 months ago
2003
ACM
We introduce and analyze the ground bounce due to power mode transition in power gating structures. To reduce the ground bounce, we propose novel power gating structures in which ...
ISLPED
2005
ACM
15 years 3 months ago
2005
ACM
This paper studies the impact on energy efficiency and thermal behavior of design style and clock-gating style in queue and array structures. These structures are major sources of...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
Lowering power is one of the greatest challenges facing the IC industry today. We present a power-aware placement method that simultaneously performs (1) activity-based register c...
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Voted
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
Power supply noise increases the circuit delay, which may lead to performance failure of a design. Decoupling capacitance (decap) addition is effective in reducing the power suppl...
ICCAD
1995
IEEE
15 years 1 months ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...