24 search results - page 4 / 5 » Gated Clock Routing Minimizing the Switched Capacitance |
GLVLSI
2000
IEEE
15 years 1 months ago
2000
IEEE
† The limits on CMOS energy dissipation imposed by subthreshold leakage currents and by wiring capacitance are investigated for CMOS generations beyond 50nm at NTRS projected loc...
75
Voted
ICCAD
1997
IEEE
15 years 1 months ago
1997
IEEE
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
62
Voted
FPGA
2005
ACM
15 years 3 months ago
2005
ACM
Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configur...
ICCAD
2004
IEEE
15 years 6 months ago
2004
IEEE
Power is an increasingly important design constraint for FPGAs in nanometer technologies. Because interconnect power is dominant in FPGAs, we design Vdd-programmable interconnect ...
93
Voted
ICCAD
1995
IEEE
15 years 1 months ago
1995
IEEE
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...