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ISCAS
2005
IEEE
146views Hardware» more  ISCAS 2005»
15 years 7 months ago
A novel approach for network on chip emulation
— Current Systems-On-Chip execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon...
Nicolas Genko, David Atienza, Giovanni De Micheli,...
117
Voted
ICML
1997
IEEE
16 years 2 months ago
Predicting Multiprocessor Memory Access Patterns with Learning Models
Machine learning techniques are applicable to computer system optimization. We show that shared memory multiprocessors can successfully utilize machine learning algorithms for mem...
M. F. Sakr, Steven P. Levitan, Donald M. Chiarulli...
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
14 years 11 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt
106
Voted
SPDP
1991
IEEE
15 years 5 months ago
Local vs. global memory in the IBM RP3: experiments and performance modelling
A number of experiments regarding the placement of instructions, private data and shared data in the Non-Uniform-Memory-Access multiprocessor, RP3 has been performed. Three Scient...
Mats Brorsson
92
Voted
TC
2008
15 years 1 months ago
An Efficient and Deadlock-Free Network Reconfiguration Protocol
Component failures and planned component replacements cause changes in the topology and routing paths supplied by the interconnection network of a parallel processor system over ti...
Olav Lysne, José Miguel Montañana, J...