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SENSYS
2006
ACM
15 years 9 months ago
Data compression algorithms for energy-constrained devices in delay tolerant networks
Sensor networks are fundamentally constrained by the difficulty and energy expense of delivering information from sensors to sink. Our work has focused on garnering additional si...
Christopher M. Sadler, Margaret Martonosi
135
Voted
DAC
2007
ACM
16 years 4 months ago
IPR: An Integrated Placement and Routing Algorithm
Abstract-- In nanometer-scale VLSI technologies, several interconnect issues like routing congestion and interconnect delay have become the main concerns in placement. However, all...
Min Pan, Chris C. N. Chu
SARA
2009
Springer
15 years 10 months ago
Automated Redesign with the General Redesign Engine
: Given a system design (SD), a key task is to optimize this design to reduce the probability of catastrophic failures. We consider the task of redesigning an SD to minimize the pr...
Alexander Feldman, Gregory M. Provan, Johan de Kle...
115
Voted
ICCAD
1994
IEEE
82views Hardware» more  ICCAD 1994»
15 years 7 months ago
A timing analysis algorithm for circuits with level-sensitive latches
For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the mo...
Jin-fuw Lee, Donald T. Tang, C. K. Wong
DAC
2004
ACM
16 years 4 months ago
A SAT-based algorithm for reparameterization in symbolic simulation
Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one para...
Pankaj Chauhan, Edmund M. Clarke, Daniel Kroening