1862 search results - page 105 / 373 » General Architecture for Hardware Implementation of Genetic ... |
109
Voted
DAC
2002
ACM
16 years 4 months ago
2002
ACM
In this paper, we present a flexible accelerator designed for networking applications. The accelerator can be utilized efficiently by a variety of Network Processor designs. Most ...
155
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DATE
2006
IEEE
15 years 9 months ago
2006
IEEE
This paper presents an Application Specific Instruction Set Processor (ASIP) design for the implementation of a class of nonlinear image processing algorithms, the Retinex-like fi...
103
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ASAP
2009
IEEE
16 years 17 days ago
2009
IEEE
—In this paper we consider a multiresolution filter and its realization on the Cell BE and GPUs. We not only present common and specific optimization strategies undertaken for ...
142
Voted
IEEEPACT
2006
IEEE
15 years 9 months ago
2006
IEEE
Transactional memory is an attractive design concept for scalable multiprocessors because it offers efficient lock-free synchronization and greatly simplifies parallel software....
133
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DATE
2003
IEEE
15 years 8 months ago
2003
IEEE
This paper presents a novel source code transformation for control flow optimizationcalled loop nest splitting which minimizes the number of executed if-statements in loop nests ...