1862 search results - page 109 / 373 » General Architecture for Hardware Implementation of Genetic ... |
126
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CAINE
2006
15 years 4 months ago
2006
The synergy of software and hardware leads to efficient application expression profile (AEP) not only in terms of execution time and energy but also optimal architecture usage. We...
123
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SIPS
2007
IEEE
15 years 9 months ago
2007
IEEE
In this paper, we investigate the efficient software implementations of the Montgomery modular multiplication algorithm on a multi-core system. A HW/SW co-design technique is use...
186
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ITC
2003
IEEE
15 years 8 months ago
2003
IEEE
This paper describes the implementation of a test pattern language using STIL [1], the IEEE Standard Test Interface Language (1450-1999), in a next generation, open architecture A...
149
Voted
CODES
2010
IEEE
15 years 5 days ago
2010
IEEE
This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant realtime distributed embedded systems used for safe...
109
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DAC
2008
ACM
16 years 4 months ago
2008
ACM
Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. T...