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126
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CODES
2007
IEEE
15 years 9 months ago
Performance and resource optimization of NoC router architecture for master and slave IP cores
System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized ...
Glenn Leary, Krishna Mehta, Karam S. Chatha
139
Voted
VLSID
2006
IEEE
158views VLSI» more  VLSID 2006»
15 years 9 months ago
Programmable LDPC Decoder Based on the Bubble-Sort Algorithm
Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardw...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
114
Voted
INTEGRATION
2007
98views more  INTEGRATION 2007»
15 years 3 months ago
Hashchip: A shared-resource multi-hash function processor architecture on FPGA
The ubiquitous presence of mobile devices and the demand for better performance and efficiency have motivated research into embedded implementations of cryptography algorithms. I...
T. S. Ganesh, Michael T. Frederick, T. S. B. Sudar...
CODES
2005
IEEE
15 years 9 months ago
An architectural level design methodology for embedded face detection
Face detection and recognition research has attracted great attention in recent years. Automatic face detection has great potential in a large array of application areas, includin...
Vida Kianzad, Sankalita Saha, Jason Schlessman, Ga...
118
Voted
EUROSYS
2010
ACM
15 years 8 months ago
NOVA: a microhypervisor-based secure virtualization architecture
The availability of virtualization features in modern CPUs has reinforced the trend of consolidating multiple guest operating systems on top of a hypervisor in order to improve pl...
Udo Steinberg, Bernhard Kauer