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DATE
2010
IEEE
156views Hardware» more  DATE 2010»
15 years 8 months ago
Domain specific architecture for next generation wireless communication
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
Botao Zhang, Hengzhu Liu, Heng Zhao, Fangzheng Mo,...
119
Voted
IPPS
2006
IEEE
15 years 9 months ago
An optimal architecture for a DDC
Digital Down Conversion (DDC) is an algorithm, used to lower the amount of samples per second by selecting a limited frequency band out of a stream of samples. A possible DDC algo...
Tjerk Bijlsma, Pascal T. Wolkotte, Gerard J. M. Sm...
ANCS
2005
ACM
15 years 9 months ago
Segmented hash: an efficient hash table implementation for high performance networking subsystems
Hash tables provide efficient table implementations, achieving O(1), query, insert and delete operations at low loads. However, at moderate or high loads collisions are quite freq...
Sailesh Kumar, Patrick Crowley
119
Voted
ISCAS
2005
IEEE
129views Hardware» more  ISCAS 2005»
15 years 9 months ago
A reconfigurable architecture for scanning biosequence databases
—Unknown protein sequences are often compared to a set of known sequences (a database scan) to detect functional similarities. Even though efficient dynamic programming algorithm...
Timothy F. Oliver, Bertil Schmidt, Douglas L. Mask...
FPL
2001
Springer
107views Hardware» more  FPL 2001»
15 years 8 months ago
Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays
In this paper we present a new method of integrating the placement and routing stages in the physical design of channel-based architectures, and present the first implementation o...
John Karro, James P. Cohoon