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95
Voted
FCCM
2008
IEEE
115views VLSI» more  FCCM 2008»
15 years 10 months ago
Simultaneous Retiming and Placement for Pipelined Netlists
Although pipelining or C-slowing an FPGA-based application can potentially dramatically improve the performance, this poses a question for conventional reconfigurable architecture...
Kenneth Eguro, Scott Hauck
DATE
2006
IEEE
88views Hardware» more  DATE 2006»
15 years 9 months ago
Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures
Temporal partitioning techniques are useful to implement large and complex applications, which can be split into partitions in FPGA devices. In order to minimize resources, each o...
Paulo Sérgio B. do Nascimento, Manoel Euseb...
ASAP
2010
IEEE
315views Hardware» more  ASAP 2010»
15 years 1 months ago
A compact FPGA-based architecture for elliptic curve cryptography over prime fields
Abstract--This paper proposes an FPGA-based applicationspecific elliptic curve processor over a prime field. This research targets applications for which compactness is more import...
Jo Vliegen, Nele Mentens, Jan Genoe, An Braeken, S...
121
Voted
DAC
2001
ACM
16 years 4 months ago
Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers
: Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concu...
Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook K...
96
Voted
ICCAD
1997
IEEE
94views Hardware» more  ICCAD 1997»
15 years 7 months ago
PRIMA: passive reduced-order interconnect macromodeling algorithm
— This paper describes an algorithm for generating provably passive reduced-order N-port models for RLC interconnect circuits. It is demonstrated that, in addition to macromodel ...
Altan Odabasioglu, Mustafa Celik, Lawrence T. Pile...