Sciweavers

1862 search results - page 128 / 373
» General Architecture for Hardware Implementation of Genetic ...
Sort
View
TEC
2002
119views more  TEC 2002»
15 years 3 months ago
Graph-based evolutionary design of arithmetic circuits
Abstract--In this paper, we present an efficient graph-based evolutionary optimization technique called evolutionary graph generation (EGG) and the proposed approach is applied to ...
Dingjun Chen, Takafumi Aoki, Naofumi Homma, Toshik...
114
Voted
DAC
2006
ACM
15 years 9 months ago
DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip
A novel routing algorithm, namely dynamic XY (DyXY) routing, is proposed for NoCs to provide adaptive routing and ensure deadlock-free and livelock-free routing at the same time. ...
Ming Li, Qing-An Zeng, Wen-Ben Jone
106
Voted
FPL
1998
Springer
107views Hardware» more  FPL 1998»
15 years 7 months ago
Modular Exponent Realization on FPGAs
The article describes modular exponent calculations used widely in cryptographic key exchange protocols. The measures for hardware consumption and execution speed based on argument...
Juri Põldre, Kalle Tammemäe, Marek Man...
162
Voted
FPL
2008
Springer
111views Hardware» more  FPL 2008»
15 years 5 months ago
Hyperreconfigurable architectures
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit the changing needs of a computation during run time. The increa...
Sebastian Lange, Martin Middendorf
SIGCOMM
2009
ACM
15 years 10 months ago
Optimizing the BSD routing system for parallel processing
The routing architecture of the original 4.4BSD [3] kernel has been deployed successfully without major design modification for over 15 years. In the unified routing architectur...
Qing Li, Kip Macy