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88
Voted
DSD
2003
IEEE
15 years 2 months ago
2003
IEEE
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
80
Voted
AICCSA
2007
IEEE
15 years 3 months ago
2007
IEEE
This paper discusses an approach for solving combinatorial problems by combining software and dynamically reconfigurable hardware (configware). The suggested technique avoids inst...
83
Voted
AHS
2007
IEEE
14 years 9 months ago
2007
IEEE
Online incremental evolution for a complex high-speed pattern recognition architecture has been implemented on a Xilinx Virtex-II Pro FPGA. The fitness evaluation module is entir...
79
Voted
FPL
1998
Springer
15 years 1 months ago
1998
Springer
Abstract. We present different architectures to solve Boolean satisfiability problems in instance-specific hardware. A simulation of these architectures shows that for examples fro...
76
Voted
FPL
1994
Springer
15 years 1 months ago
1994
Springer
The implementation of larger digital neural networks has not been possible due to the real-estate requirements of single neurons. We present an expandable digital architecture whic...