Sciweavers

1862 search results - page 171 / 373
» General Architecture for Hardware Implementation of Genetic ...
Sort
View
148
Voted
CODES
2005
IEEE
15 years 9 months ago
DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs
We present a new scheme for dynamic voltage and frequency scaling (DVS) for processing multimedia streams on architectures with restricted buffer sizes. The main advantage of our ...
Alexander Maxiaguine, Samarjit Chakraborty, Lothar...
120
Voted
PLDI
2004
ACM
15 years 9 months ago
Vectorization for SIMD architectures with alignment constraints
When vectorizing for SIMD architectures that are commonly employed by today’s multimedia extensions, one of the new challenges that arise is the handling of memory alignment. Pr...
Alexandre E. Eichenberger, Peng Wu, Kevin O'Brien
148
Voted
INFOCOM
2007
IEEE
15 years 10 months ago
Iterative Scheduling Algorithms
— The input-queued switch architecture is widely used in Internet routers due to its ability to run at very high line speeds. A central problem in designing an input-queued switc...
Mohsen Bayati, Balaji Prabhakar, Devavrat Shah, Ma...
124
Voted
GLVLSI
2006
IEEE
126views VLSI» more  GLVLSI 2006»
15 years 9 months ago
Hardware/software partitioning of operating systems: a behavioral synthesis approach
In this paper we propose a hardware real time operating system (HW-RTOS) solution that makes use of a dedicated hardware in order to replace the standard support provided by the P...
Sathish Chandra, Francesco Regazzoni, Marcello Laj...
139
Voted
AR
2008
97views more  AR 2008»
15 years 3 months ago
Modular Architecture for Humanoid Walking Pattern Prototyping and Experiments
In this paper we describe the use of design patterns as a basis for creating a Humanoid Walking Pattern Generator Software having a modular architecture. This architecture made po...
Olivier Stasse, Björn Verrelst, Pierre-Brice ...