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139
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CF
2005
ACM
15 years 5 months ago
Dynamic loop pipelining in data-driven architectures
Data-driven array architectures seem to be important alternatives for coarse-grained reconfigurable computing platforms. Their use has provided performance improvements over micro...
João M. P. Cardoso
131
Voted
EUROPAR
2000
Springer
15 years 7 months ago
BitValue Inference: Detecting and Exploiting Narrow Bitwidth Computations
We present a compiler algorithm called BitValue, which can discover both unused and constant bits in dusty-deck C programs. BitValue uses forward and backward dataflow analyses, ge...
Mihai Budiu, Majd Sakr, Kip Walker, Seth Copen Gol...
110
Voted
ISPD
2004
ACM
171views Hardware» more  ISPD 2004»
15 years 9 months ago
Structured ASIC, evolution or revolution?
This paper describes the structured ASIC technology and impacts to the implementation flow. With an optimized and programmable structure, the structured ASIC technology indeed int...
Kun-Cheng Wu, Yu-Wen Tsai
112
Voted
ISCAS
1995
IEEE
91views Hardware» more  ISCAS 1995»
15 years 7 months ago
An FPGA Based Reconfigurable Coprocessor Board Utilizing a Mathematics of Arrays
Abstract -- Work in progress at the University of Missouri-Rolla on hardware assists for high performance computing is presented. This research consists of a novel field programmab...
W. Eatherton, J. Kelly, T. Schiefelbein, H. Pottin...
132
Voted
ANCS
2007
ACM
15 years 7 months ago
Frame-aggregated concurrent matching switch
Network operators need high-capacity router architectures that can offer scalability, provide throughput and performance guarantees, and maintain packet ordering. However, previou...
Bill Lin, Isaac Keslassy