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INFOSCALE
2006
ACM
15 years 7 months ago
Scalable hardware accelerator for comparing DNA and protein sequences
Abstract— Comparing genetic sequences is a well-known problem in bioinformatics. Newly determined sequences are being compared to known sequences stored in databases in order to ...
Philippe Faes, Bram Minnaert, Mark Christiaens, Er...
COMPUTING
2004
204views more  COMPUTING 2004»
15 years 1 months ago
Image Registration by a Regularized Gradient Flow. A Streaming Implementation in DX9 Graphics Hardware
The presented image registration method uses a regularized gradient flow to correlate the intensities in two images. Thereby, an energy functional is successively minimized by des...
Robert Strzodka, Marc Droske, Martin Rumpf
157
Voted
FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
15 years 2 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
99
Voted
SC
2009
ACM
15 years 8 months ago
Implementing a high-volume, low-latency market data processing system on commodity hardware using IBM middleware
A stock market data processing system that can handle high data volumes at low latencies is critical to market makers. Such systems play a critical role in algorithmic trading, ri...
Xiaolan J. Zhang, Henrique Andrade, Bugra Gedik, R...
IPPS
2000
IEEE
15 years 6 months ago
A Novel Superscalar Architecture for Fast DCT Implementation
This paper presents a new superscalar architecture for fast discrete cosine transform (DCT). Comparing with the general SIMD architecture, it speeds up the DCT computation by a fac...
Zhang Yong, Min Zhang