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134
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VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
16 years 3 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
TC
2008
15 years 3 months ago
Cryptanalysis with COPACOBANA
Cryptanalysis of ciphers usually involves massive computations. The security parameters of cryptographic algorithms are commonly chosen so that attacks are infeasible with availabl...
Tim Güneysu, Timo Kasper, Martin Novotn&yacut...
149
Voted
ARC
2008
Springer
95views Hardware» more  ARC 2008»
15 years 5 months ago
The Instruction-Set Extension Problem: A Survey
Over the last years, we have witnessed the increased use of Application-Specific Instruction-Set Processors (ASIPs). These ASIPs are processors that have a customizable instruction...
Carlo Galuzzi, Koen Bertels
123
Voted
IEEEPACT
2009
IEEE
15 years 10 months ago
Interprocedural Load Elimination for Dynamic Optimization of Parallel Programs
Abstract—Load elimination is a classical compiler transformation that is increasing in importance for multi-core and many-core architectures. The effect of the transformation is ...
Rajkishore Barik, Vivek Sarkar
ISCAS
2007
IEEE
180views Hardware» more  ISCAS 2007»
15 years 9 months ago
Characterization of a Fault-tolerant NoC Router
— With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip (SoC) and multicore ...
Sumit D. Mediratta, Jeffrey T. Draper