Sciweavers

1862 search results - page 250 / 373
» General Architecture for Hardware Implementation of Genetic ...
Sort
View
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
15 years 7 months ago
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
Imran Ahmed, Tughrul Arslan
124
Voted
BIRTHDAY
2003
Springer
15 years 8 months ago
Parallel Digital Halftoning by Error-Diffusion
Digital halftoning, or dithering, is the technique commonly used to render a color or grayscale image on a printer, a computer monitor or other bi-level displays. A particular hal...
Panagiotis Takis Metaxas
152
Voted
FPGA
2004
ACM
158views FPGA» more  FPGA 2004»
15 years 9 months ago
A novel coarse-grain reconfigurable data-path for accelerating DSP kernels
In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...
Michalis D. Galanis, George Theodoridis, Spyros Tr...
126
Voted
CIDR
2007
144views Algorithms» more  CIDR 2007»
15 years 5 months ago
Cache-Oblivious Query Processing
We propose a radical approach to relational query processing that aims at automatically and consistently achieving a good performance on any memory hierarchy. We believe this auto...
Bingsheng He, Qiong Luo
141
Voted
ICCAD
1999
IEEE
84views Hardware» more  ICCAD 1999»
15 years 7 months ago
OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic
The optimal state minimization problem is to select a reduced state machine having the best logic implementation over all possible state reductions and encodings. A recent algorit...
Robert M. Fuhrer, Steven M. Nowick