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122
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CGO
2003
IEEE
15 years 8 months ago
2003
IEEE
Many processor architectures provide a set of addressing modes in their address generation units. For example DSPs (digital signal processors) have powerful addressing modes for e...
142
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DAC
2007
ACM
15 years 7 months ago
2007
ACM
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...
150
Voted
VLSI
2010
Springer
15 years 1 months ago
2010
Springer
—In this paper, we introduce a design methodology to implement low-complexity and high-speed digital Finite Impulse Response (FIR) filters. Since FIR filters suffer from a larg...
157
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DASIP
2010
14 years 10 months ago
2010
Nowadays, the design flow of complex signal processing embedded systems starts with a specification of the application by means of a large and sequential program (usually in C/C++...
103
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ISCAS
2007
IEEE
15 years 9 months ago
2007
IEEE
— We present theory, design and measurement results for an on-line histogram equalization algorithm implemented on a 750MS/s 6b flash analog to digital converter in standard 0.3...