1862 search results - page 27 / 373 » General Architecture for Hardware Implementation of Genetic ... |
ICCD
1994
IEEE
15 years 6 months ago
1994
IEEE
Systems for multi-level logic optimization are usually based on a set of specialized, loosely-related transformations which work on a network representation. The sequence of trans...
117
Voted
FCCM
2005
IEEE
15 years 7 months ago
2005
IEEE
The security of the most popular asymmetric cryptographic scheme RSA depends on the hardness of factoring large numbers. The best known method for factorization large integers is ...
96
Voted
DAC
2005
ACM
15 years 3 months ago
2005
ACM
This paper presents an efficient hardware architecture of an on-chip logic minimization coprocessor. The proposed architecture employs TCAM cells to provide fastest and memory eï¬...
108
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ISCAS
2003
IEEE
15 years 7 months ago
2003
IEEE
—This paper presents high-speed parallel Reed–Solomon (RS) (255,239) decoder architecture using modified Euclidean algorithm for the high-speed multigigabit-per-second fiber op...
AHS
2006
IEEE
15 years 8 months ago
2006
IEEE
The discrete wavelet Transform (DWT), as defined by the Image Compression Standard JPEG-2000, is one of the most time-consuming computations which cannot be efficiently executed o...