We investigate and develop energy-efficient strategies for deployment of wireless sensor networks (WSN) for the purpose of monitoring some phenomenon of interest in a coverage reg...
Irregular applications frequently exhibit poor performance on contemporary computer architectures, in large part because of their inefficient use of the memory hierarchy. Runtime ...
In this paper, we overview general hardware architecture and a programming model of SRC-6ETM reconfigurable computers, and compare the performance of the SRC-6E machine vs. IntelÂ...
Osman Devrim Fidanci, Daniel S. Poznanovic, Kris G...
High performance processors use checkpointing to rapidly recover from branch mispredictions and possibly other exceptions. We demonstrate that conventional checkpointing becomes u...
—While computing speed continues increasing rapidly, data-access technology is lagging behind. Data-access delay, not the processor speed, becomes the leading performance bottlen...