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121
Voted
DSD
2009
IEEE
147views Hardware» more  DSD 2009»
15 years 5 months ago
A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computat...
Abdulkadir Akin, Yigit Dogan, Ilker Hamzaoglu
85
Voted
DATE
2007
IEEE
78views Hardware» more  DATE 2007»
15 years 8 months ago
Hardware scheduling support in SMP architectures
In this paper we propose a hardware real time operating system (HW-RTOS) that implements the OS layer in a dual-processor SMP architecture. Intertask communication is specified b...
André C. Nácul, Francesco Regazzoni,...
98
Voted
GECCO
2007
Springer
187views Optimization» more  GECCO 2007»
15 years 8 months ago
Defining implicit objective functions for design problems
In many design tasks it is difficult to explicitly define an objective function. This paper uses machine learning to derive an objective in a feature space based on selected examp...
Sean Hanna
GECCO
2007
Springer
179views Optimization» more  GECCO 2007»
15 years 8 months ago
A destructive evolutionary process: a pilot implementation
This paper describes the application of evolutionary search to the problem of Flash memory wear-out. The operating parameters of Flash memory are notoriously difficult to determin...
Joe Sullivan, Conor Ryan
151
Voted
ERSA
2009
147views Hardware» more  ERSA 2009»
14 years 11 months ago
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Kylan Robinson, José G. Delgado-Frias