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SIGMETRICS
2011
ACM
178views Hardware» more  SIGMETRICS 2011»
14 years 6 months ago
Soft error benchmarking of L2 caches with PARMA
The amount of charge stored in an SRAM cell shrinks rapidly with each technology generation thus increasingly exposing caches to soft errors. Benchmarking the FIT rate of caches d...
Jinho Suh, Mehrtash Manoochehri, Murali Annavaram,...
IPSN
2010
Springer
15 years 10 months ago
High-resolution, low-power time synchronization an oxymoron no more
We present Virtual High-resolution Time (VHT), a powerproportional time-keeping service that offers a baseline power draw of a low-speed clock (e.g. 32 kHz crystal), but provides...
Thomas Schmid, Prabal Dutta, Mani B. Srivastava
CODES
2005
IEEE
15 years 9 months ago
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
Girish Venkataramani, Tiberiu Chelcea, Seth Copen ...
DRM
2006
Springer
15 years 7 months ago
The problem with rights expression languages
In this paper we consider the functionality that a rights expression language (REL) should provide within a digital rights management (DRM) environment. We begin by noting the dea...
Pramod A. Jamkhedkar, Gregory L. Heileman, Iv&aacu...
ARITH
2001
IEEE
15 years 7 months ago
Computer Arithmetic-A Processor Architect's Perspective
The Instruction Set Architecture (ISA) of a programmable processor is the native languageof the machine. It defines the set of operations and resourcesthat are optimized for that ...
Ruby B. Lee