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ISCAS
2007
IEEE
161views Hardware» more  ISCAS 2007»
15 years 8 months ago
Hardware Architecture of a Parallel Pattern Matching Engine
Abstract— Several network security and QoS applications require detecting multiple string matches in the packet payload by comparing it against predefined pattern set. This proc...
Meeta Yadav, Ashwini Venkatachaliah, Paul D. Franz...
127
Voted
DSD
2009
IEEE
387views Hardware» more  DSD 2009»
15 years 8 months ago
Architecture and DSP Implementation of a DVB-S2 Baseband Demodulator
—This paper presents the design and implementation of a baseband demodulator for DVB-S2 satellite receivers. In order to meet the requirements of different complex and multidomai...
Panayiotis Savvopoulos, Nikolaos Papandreou, Theod...
ISCAS
2007
IEEE
93views Hardware» more  ISCAS 2007»
15 years 8 months ago
VLSI Implementation of a Lattice-Reduction Algorithm for Multi-Antenna Broadcast Precoding
Abstract— This paper describes the first VLSI implementation of lattice reduction (LR) aided multi-antenna broadcast precoding with vector perturbation. The considered LR scheme...
Andreas Burg, Dominik Seethaler, Gerald Matz
ICES
2010
Springer
106views Hardware» more  ICES 2010»
14 years 12 months ago
The Use of Genetic Algorithm to Reduce Power Consumption during Test Application
Abstract. In this paper it is demonstrated how two issues from the area of testing electronic components can be merged and solved by means of a genetic algorithm. The two issues ar...
Jaroslav Skarvada, Zdenek Kotásek, Josef St...
ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
15 years 11 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda