1862 search results - page 32 / 373 » General Architecture for Hardware Implementation of Genetic ... |
135
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ASPDAC
2007
ACM
15 years 5 months ago
2007
ACM
- This paper presents a real time programmable irregular Low Density Parity Check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for fram...
105
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GLVLSI
2005
IEEE
15 years 7 months ago
2005
IEEE
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
103
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DATE
2002
IEEE
15 years 6 months ago
2002
IEEE
Third generation’s wireless communications systems comprise advanced signal processing algorithms that increase the computational requirements more than ten-fold over 2G’s sys...
101
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SASP
2008
IEEE
15 years 8 months ago
2008
IEEE
— With the increasing popularity of MP3 audio, there is a need to develop cost and power efficient architectures for the MP3 encoder and decoder. This paper describes dedicated ...
129
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GECCO
2006
Springer
15 years 5 months ago
2006
Springer
The importance of mutation varies across evolutionary computation domains including: genetic programming, evolution strategies, and genetic algorithms. In the genetic programming ...