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IJNSEC
2008
106views more  IJNSEC 2008»
15 years 1 months ago
Parallel Hardware Architectures for the Cryptographic Tate Pairing
Identity-based cryptography uses pairing functions,which are sophisticated bilinear maps defined on elliptic curves.Computing pairings efficiently in software is presently a relev...
Guido Marco Bertoni, Luca Breveglieri, Pasqualina ...
DATE
2010
IEEE
125views Hardware» more  DATE 2010»
15 years 7 months ago
pSHS: A scalable parallel software implementation of Montgomery multiplication for multicore systems
—Parallel programming techniques have become one of the great challenges in the transition from single-core to multicore architectures. In this paper, we investigate the parallel...
Zhimin Chen, Patrick Schaumont
WIA
2000
Springer
15 years 5 months ago
Fast Implementations of Automata Computations
Abstract. In 6], G. Myers describes a bit-vector algorithm to compute the edit distance between strings. The algorithm converts an input sequence to an output sequence in a paralle...
Anne Bergeron, Sylvie Hamel
DCC
2007
IEEE
16 years 1 months ago
Algorithms and Hardware Structures for Unobtrusive Real-Time Compression of Instruction and Data Address Traces
Instruction and data address traces are widely used by computer designers for quantitative evaluations of new architectures and workload characterization, as well as by software de...
Milena Milenkovic, Aleksandar Milenkovic, Martin B...
ASPDAC
2001
ACM
100views Hardware» more  ASPDAC 2001»
15 years 5 months ago
Low power implementation of a turbo-decoder on programmable architectures
Low Power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signal processing units in mobile terminal ar...
Frank Gilbert, Alexander Worm, Norbert Wehn