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FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
15 years 7 months ago
Divide and concatenate: a scalable hardware architecture for universal MAC
We present a cryptographic architecture optimization technique called divide-and-concatenate based on two observations: (i) the area of a multiplier and associated data path decre...
Bo Yang, Ramesh Karri, David A. McGrew
SASP
2009
IEEE
238views Hardware» more  SASP 2009»
15 years 8 months ago
Hardware acceleration of multi-view face detection
—This paper presents a parallelized architecture for hardware acceleration of multi-view face detection. In our architecture, the multi-view face detection system generates rotat...
Junguk Cho, Bridget Benson, Ryan Kastner
CGO
2005
IEEE
15 years 7 months ago
Optimizing Sorting with Genetic Algorithms
The growing complexity of modern processors has made the generation of highly efficient code increasingly difficult. Manual code generation is very time consuming, but it is oft...
Xiaoming Li, María Jesús Garzar&aacu...
ENC
2004
IEEE
15 years 5 months ago
On the Hardware Design of an Elliptic Curve Cryptosystem
We present a hardware architecture for an Elliptic Curve Cryptography System performing the three basic cryptographic schemes: DH key generation, encryption and digital signature....
Miguel Morales-Sandoval, Claudia Feregrino Uribe
EDBT
2010
ACM
155views Database» more  EDBT 2010»
15 years 5 months ago
Suffix tree construction algorithms on modern hardware
Suffix trees are indexing structures that enhance the performance of numerous string processing algorithms. In this paper, we propose cache-conscious suffix tree construction algo...
Dimitris Tsirogiannis, Nick Koudas