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FPGA
2004
ACM
174views FPGA» more  FPGA 2004»
15 years 7 months ago
A compiled accelerator for biological cell signaling simulations
The simulation of large systems of biochemical reactions is a key part of research into molecular signaling and information processing in biological cells. However, it can be impr...
John F. Keane, Christopher Bradley, Carl Ebeling
ICCD
2005
IEEE
165views Hardware» more  ICCD 2005»
15 years 10 months ago
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation
Presently, Architecture Description Languages (ADLs) are widely used to raise the abstraction level of the design space exploration of Application Specific Instruction-set Proces...
Ernst Martin Witte, Anupam Chattopadhyay, Oliver S...
GECCO
2010
Springer
158views Optimization» more  GECCO 2010»
15 years 6 months ago
A genetic algorithm to improve linux kernel performance on resource-constrained devices
As computers become increasingly mobile, users demand more functionality, longer battery-life, and better performance from mobile devices. In response, chipset fabricators are foc...
James Kukunas, Robert D. Cupper, Gregory M. Kapfha...
MICRO
2002
IEEE
121views Hardware» more  MICRO 2002»
15 years 1 months ago
Convergent scheduling
Convergent scheduling is a general framework for instruction scheduling and cluster assignment for parallel, clustered architectures. A convergent scheduler is composed of many ind...
Walter Lee, Diego Puppin, Shane Swenson, Saman P. ...
INDOCRYPT
2010
Springer
14 years 12 months ago
One Byte per Clock: A Novel RC4 Hardware
RC4, the widely used stream cipher, is well known for its simplicity and ease of implementation in software. In case of a special purpose hardware designed for RC4, the best known ...
Sourav Sengupta, Koushik Sinha, Subhamoy Maitra, B...