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FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
15 years 6 months ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor
ISLPED
1998
ACM
84views Hardware» more  ISLPED 1998»
15 years 6 months ago
Low power architecture of the soft-output Viterbi algorithm
CT This paper investigates the low power implementation issues of the soft-output Viterbi algorithm (SOVA), a building block for turbo codes. By briefly explaining the theory of t...
David Garrett, Mircea R. Stan
SIPS
2008
IEEE
15 years 8 months ago
Unified decoder architecture for LDPC/turbo codes
Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon li...
Yang Sun, Joseph R. Cavallaro
TOG
2008
145views more  TOG 2008»
15 years 1 months ago
Real-time KD-tree construction on graphics hardware
We present an algorithm for constructing kd-trees on GPUs. This algorithm achieves real-time performance by exploiting the GPU's streaming architecture at all stages of kd-tr...
Kun Zhou, Qiming Hou, Rui Wang 0004, Baining Guo
GECCO
2008
Springer
103views Optimization» more  GECCO 2008»
15 years 3 months ago
Empirical investigations on parallel competent genetic algorithms
This paper empirically investigates parallel competent genetic algorithms (cGAs) [4]. cGAs, such as BOA [21], LINCGA [15], D5 -GA [28], can solve GA-difficult problems by automati...
Miwako Tsuji, Masaharu Munetomo, Kiyoshi Akama