1862 search results - page 47 / 373 » General Architecture for Hardware Implementation of Genetic ... |
107
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GECCO
2007
Springer
15 years 8 months ago
2007
Springer
We present what we believe is the first attempt to physically reconstruct the exploratory mechanism of genetic regulatory networks. Feedback plays a crucial role during developme...
109
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ARC
2008
Springer
15 years 4 months ago
2008
Springer
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
ICCD
1993
IEEE
15 years 6 months ago
1993
IEEE
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
103
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ASAP
2003
IEEE
15 years 7 months ago
2003
IEEE
This paper introduces basic principles for extending the classical systolic synthesis methodology to multi-dimensional time. Multi-dimensional scheduling enables complex algorithm...
ICNC
2005
Springer
15 years 7 months ago
2005
Springer
This paper proposes an improved genetic algorithm for producing aesthetically pleasing drawings of general undirected graphs. Previous undirected graph drawing algorithms draw larg...