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DAC
2006
ACM
16 years 2 months ago
An efficient and versatile scheduling algorithm based on SDC formulation
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
Jason Cong, Zhiru Zhang
STTT
2011
195views more  STTT 2011»
14 years 9 months ago
Parallel probabilistic model checking on general purpose graphics processors
We present algorithms for parallel probabilistic model checking on general purpose graphic processing units (GPGPUs). Our improvements target the numerical components of the tradit...
Dragan Bosnacki, Stefan Edelkamp, Damian Sulewski,...
IPPS
1999
IEEE
15 years 6 months ago
Leonardo and Discipulus Simplex: An Autonomous, Evolvable Six-Legged Walking Robot
Evolutionary systems based on genetic algorithms GAs are common nowadays. One of the recent uses of such systems is in the burgeoning eld of evolvable hardware which involves, amo...
Gilles Ritter, Jean-Michel Puiatti, Eduardo Sanche...
SBACPAD
2007
IEEE
130views Hardware» more  SBACPAD 2007»
15 years 8 months ago
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh
ISCAS
2005
IEEE
99views Hardware» more  ISCAS 2005»
15 years 7 months ago
On the implementation of 128-pt FFT/IFFT for high-performance WPAN
- This paper deals with the efficient realization of a 128-pt FFT/IFFT processor for application in IEEE 802.15.3a standard. The 128-pt FFT/IFFT architecture has been designed by d...
C. Huggett, K. Maharatna, K. Paul