1862 search results - page 53 / 373 » General Architecture for Hardware Implementation of Genetic ... |
DATE
2007
IEEE
15 years 8 months ago
2007
IEEE
Weaknesses have recently been found in the widely used cryptographic hash functions SHA-1 and MD5. A potential alternative for these algorithms is the Whirlpool hash function, whi...
115
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GLVLSI
2005
IEEE
15 years 7 months ago
2005
IEEE
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
114
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PPOPP
2009
ACM
16 years 2 months ago
2009
ACM
In a previous paper we show how the FLAME methods and tools provide a solution to compute dense dense linear algebra operations on a multi-GPU platform with reasonable performance...
ISCAS
1993
IEEE
15 years 6 months ago
1993
IEEE
- A novel VLSI implementation of the Viterbi algorithm based on a cascade architecture is presented. Survivor sequence memory management is implemented using a new single read poin...
107
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SAC
2009
ACM
15 years 8 months ago
2009
ACM
Decision trees are widely disseminated as an effective solution for classification tasks. Decision tree induction algorithms have some limitations though, due to the typical strat...