1862 search results - page 55 / 373 » General Architecture for Hardware Implementation of Genetic ... |
ISCAS
2006
IEEE
15 years 8 months ago
2006
IEEE
— In this paper an architecture, signal reconstruction algorithm and first-ever implementation of an asynchronous delta-sigma converter are presented. The signal reconstruction ...
107
click to vote
FPL
2010
Springer
14 years 12 months ago
2010
Springer
Abstract--The second round of the NIST-run public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). This paper present...
112
click to vote
DATE
2008
IEEE
15 years 8 months ago
2008
IEEE
In this paper, we use the generalized binary de Bruijn (GBDB) graph as a scalable and efficient network topology for an on-chip communication network. Using just two-layer wiring,...
129
click to vote
ISLPED
2003
ACM
15 years 7 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
107
click to vote
DATE
2006
IEEE
15 years 8 months ago
2006
IEEE
Multimedia and communication algorithms from embedded system domain often make extensive use of floating-point arithmetic. Due to the complexity and expense of the floating-poin...