Sciweavers

1862 search results - page 56 / 373
» General Architecture for Hardware Implementation of Genetic ...
Sort
View
BMCBI
2011
14 years 5 months ago
A hierarchical Bayesian network approach for linkage disequilibrium modeling and data-dimensionality reduction prior to genome-w
Background: Discovering the genetic basis of common genetic diseases in the human genome represents a public health issue. However, the dimensionality of the genetic data (up to 1...
Raphael Mourad, Christine Sinoquet, Philippe Leray
AFRICACRYPT
2009
Springer
14 years 11 months ago
Efficient Acceleration of Asymmetric Cryptography on Graphics Hardware
Graphics processing units (GPU) are increasingly being used for general purpose computing. We present implementations of large integer modular exponentiation, the core of public-ke...
Owen Harrison, John Waldron
ASPDAC
2005
ACM
132views Hardware» more  ASPDAC 2005»
15 years 4 months ago
Automatic synthesis and scheduling of multirate DSP algorithms
- To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of mult...
Ying Yi, Mark Milward, Sami Khawam, Ioannis Nousia...
ICES
2005
Springer
138views Hardware» more  ICES 2005»
15 years 7 months ago
A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device
Abstract. There have been introduced a number of systems with evolvable hardware on a single chip. To overcome the lack of flexibility in these systems, we propose a single-chip e...
Kyrre Glette, Jim Torresen
ASPDAC
2010
ACM
163views Hardware» more  ASPDAC 2010»
15 years 8 hour ago
A3MAP: architecture-aware analytic mapping for networks-on-chip
- In this paper, we propose a novel and global A3MAP (Architecture-Aware Analytic Mapping) algorithm applied to NoC (Networks-on-Chip) based MPSoC (Multi-Processor System-on-Chip) ...
Wooyoung Jang, David Z. Pan