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FPL
2009
Springer
156views Hardware» more  FPL 2009»
15 years 7 months ago
A highly scalable Restricted Boltzmann Machine FPGA implementation
Restricted Boltzmann Machines (RBMs) — the building block for newly popular Deep Belief Networks (DBNs) — are a promising new tool for machine learning practitioners. However,...
Sang Kyun Kim, Lawrence C. McAfee, Peter L. McMaho...
SIGGRAPH
1999
ACM
15 years 7 months ago
A Real-Time Low-Latency Hardware Light-Field Renderer
This paper describes the design and implementation of an architecture for interactively viewing static light fields with very low latency. The system was deliberately over enginee...
Matthew J. P. Regan, Gavin S. P. Miller, Steven M....
DAC
2005
ACM
16 years 4 months ago
MP core: algorithm and design techniques for efficient channel estimation in wireless applications
Channel estimation and multiuser detection are enabling technologies for future generations of wireless applications. However, sophisticated algorithms are required for accurate c...
Yan Meng, Andrew P. Brown, Ronald A. Iltis, Timoth...
TIP
2008
175views more  TIP 2008»
15 years 3 months ago
Algorithmic and Architectural Optimizations for Computationally Efficient Particle Filtering
Abstract--In this paper, we analyze the computational challenges in implementing particle filtering, especially to video sequences. Particle filtering is a technique used for filte...
Aswin C. Sankaranarayanan, Ankur Srivastava, Rama ...
DAC
2006
ACM
15 years 9 months ago
Use of C/C++ models for architecture exploration and verification of DSPs
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
David Brier, Raj S. Mitra