1862 search results - page 60 / 373 » General Architecture for Hardware Implementation of Genetic ... |
121
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DAC
2005
ACM
15 years 5 months ago
2005
ACM
This paper presents a novel synthesis algorithm that reduces the area needed for implementing multiplexers on an FPGA by an average of 18%. This is achieved by reducing the number...
153
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CF
2009
ACM
15 years 9 months ago
2009
ACM
In this paper, we compare the architectural perspectives of the Wave Field Synthesis (WFS) 3D-audio algorithm mapped on three different platforms: a General Purpose Processor (GP...
134
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GECCO
2010
Springer
15 years 6 months ago
2010
Springer
We use affine arithmetic to improve both the performance and the robustness of genetic programming for symbolic regression. During evolution, we use affine arithmetic to analyze e...
110
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APCSAC
2000
IEEE
15 years 7 months ago
2000
IEEE
Hardware square-root units require large numbers of gates even for iterative implementations. In this paper, we present four low-cost high-performance fullypipelined n-select impl...
137
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CHES
2008
Springer
15 years 5 months ago
2008
Springer
Dynamically reconfigurable systems are known to have many advantages such as area and power reduction. The drawbacks of these systems are the reconfiguration delay and the overhead...