1862 search results - page 79 / 373 » General Architecture for Hardware Implementation of Genetic ... |
102
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FPL
2003
Springer
15 years 8 months ago
2003
Springer
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
122
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JCP
2008
15 years 3 months ago
2008
Abstract--In this paper, we report some results on hardware and software co-design of an adaptive linear neuron (ADALINE) based control system. A discrete-time Proportional-Integra...
112
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ICPP
1993
IEEE
15 years 7 months ago
1993
IEEE
:. In designing application-specific bit-level architectures and in programming existing bit-level processor arrays, it is necessary to expand a word-level algorithm into its bit-...
135
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CHES
2007
Springer
15 years 7 months ago
2007
Springer
Graphics Processing Units (GPUs) present large potential performance gains within stream processing applications over the standard CPU. These performance gains are best realised wh...
139
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FPL
2009
Springer
15 years 8 months ago
2009
Springer
Although there are many neural network FPGA architectures, there is no framework for designing large, high-performance neural networks suitable for the real world. In this paper, ...