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DAC
2004
ACM
16 years 4 months ago
Synthesizing interconnect-efficient low density parity check codes
Error correcting codes are widely used in communication and storage applications. Codec complexity has usually been measured with a software implementation in mind. A recent hardw...
Marghoob Mohiyuddin, Amit Prakash, Adnan Aziz, Way...
135
Voted
ERSA
2006
133views Hardware» more  ERSA 2006»
15 years 4 months ago
An FPGA based Co-Design Architecture for MIMO Lattice Decoders
MIMO systems have attracted great attentions because of their huge capacity. The hardware implementation of MIMO decoder becomes a challenging task as the complexity of the MIMO sy...
Cao Liang, Jing Ma, Xin-Ming Huang
JUCS
2006
112views more  JUCS 2006»
15 years 3 months ago
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip
Abstract: Advances in technology now make it possible to integrate hundreds of cores (e.g. general or special purpose processors, embedded memories, application specific components...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
DATE
1999
IEEE
162views Hardware» more  DATE 1999»
15 years 7 months ago
MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
Robert P. Dick, Niraj K. Jha
ASPDAC
2007
ACM
146views Hardware» more  ASPDAC 2007»
15 years 7 months ago
Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos
Abstract-- This paper describes the stochastic model order reduction algorithm via stochastic Hermite Polynomials from the practical implementation perspective. Comparing with exis...
Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheld...