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ASAP
2008
IEEE
117views Hardware» more  ASAP 2008»
15 years 5 months ago
Reconfigurable acceleration of microphone array algorithms for speech enhancement
Microphone arrays play an important role in noise reduction and speech enhancement. Their algorithms are based on beamforming, which reduces the level of localized and ambient noi...
Ka Fai Cedric Yiu, Chun Hok Ho, Nedelko Grbic, Yao...
ASAP
2006
IEEE
106views Hardware» more  ASAP 2006»
15 years 9 months ago
Throughput Optimized SHA-1 Architecture Using Unfolding Transformation
In this paper, we analyze the theoretical delay bound of the SHA-1 algorithm and propose architectures to achieve high throughput hardware implementations which approach this boun...
Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede
IWSOC
2005
IEEE
151views Hardware» more  IWSOC 2005»
15 years 9 months ago
A Low Area and Low Power Programmable Baseband Processor Architecture
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...
Eric Tell, Anders Nilsson, Dake Liu
ICIP
2004
IEEE
16 years 4 months ago
A parallel mediated reality platform
Realtime image processing provides a general framework for robust mediated reality problems. This paper presents a realtime mediated reality system that is built upon realtime ima...
Rosco Hill, James Fung, Steve Mann
GECCO
2008
Springer
155views Optimization» more  GECCO 2008»
15 years 4 months ago
Experiments with indexed FOR-loops in genetic programming
We investigated how indexed FOR-loops, such as the ones found in procedural programming languages, can be implemented in genetic programming. We use them to train programs that le...
Gayan Wijesinghe, Victor Ciesielski