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ISCA
2005
IEEE
128views Hardware» more  ISCA 2005»
15 years 9 months ago
An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures
: The theoretical study of quantum computation has yielded efficient algorithms for some traditionally hard problems. Correspondingly, experimental work on the underlying physical...
Steven Balensiefer, Lucas Kreger-Stickles, Mark Os...
VEE
2012
ACM
187views Virtualization» more  VEE 2012»
13 years 11 months ago
DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support
Dynamic Binary Translators (DBT) and Dynamic Binary Optimization (DBO) by software are used widely for several reasons including performance, design simplification and virtualiza...
Demos Pavlou, Enric Gibert, Fernando Latorre, Anto...
144
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ICCAD
2002
IEEE
142views Hardware» more  ICCAD 2002»
16 years 7 days ago
SAT and ATPG: Boolean engines for formal hardware verification
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
Armin Biere, Wolfgang Kunz
EGH
2009
Springer
15 years 1 months ago
Efficient stream compaction on wide SIMD many-core architectures
Stream compaction is a common parallel primitive used to remove unwanted elements in sparse data. This allows highly parallel algorithms to maintain performance over several proce...
Markus Billeter, Ola Olsson, Ulf Assarsson
FPL
2003
Springer
164views Hardware» more  FPL 2003»
15 years 8 months ago
FPGA Implementations of the RC6 Block Cipher
RC6 is a symmetric-key algorithm which encrypts 128-bit plaintext blocks to 128-bit ciphertext blocks. The encryption process involves four operations: integer addition modulo 2w ,...
Jean-Luc Beuchat