Sciweavers

3119 search results - page 220 / 624
» General Default Logic
Sort
View
97
Voted
VLSID
2009
IEEE
130views VLSI» more  VLSID 2009»
16 years 1 months ago
Reversible Logic Synthesis with Output Permutation
Synthesis of reversible logic has become a very important research area. In recent years several algorithms ? heuristic as well as exact ones ? have been introduced in this area. ...
Daniel Große, Gerhard W. Dueck, Robert Wille...
119
Voted
PODS
2008
ACM
143views Database» more  PODS 2008»
16 years 28 days ago
XPath, transitive closure logic, and nested tree walking automata
We consider the navigational core of XPath, extended with two operators: the Kleene star for taking the transitive closure of path expressions, and a subtree relativisation operat...
Balder ten Cate, Luc Segoufin
LPNMR
2009
Springer
15 years 7 months ago
Relevance-Driven Evaluation of Modular Nonmonotonic Logic Programs
Modular nonmonotonic logic programs (MLPs) under the answer-set semantics have been recently introduced as an ASP formalism in which modules can receive context-dependent input fro...
Minh Dao-Tran, Thomas Eiter, Michael Fink, Thomas ...
100
Voted
DATE
2008
IEEE
121views Hardware» more  DATE 2008»
15 years 7 months ago
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthe...
Irith Pomeranz, Sudhakar M. Reddy
FPGA
2007
ACM
185views FPGA» more  FPGA 2007»
15 years 7 months ago
Power-aware FPGA logic synthesis using binary decision diagrams
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
Kevin Oo Tinmaung, David Howland, Russell Tessier