Sciweavers

3119 search results - page 261 / 624
» General Default Logic
Sort
View
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
15 years 9 months ago
Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resulting model contains only four-valued unit and zero delay logic primitives, suita...
Randal E. Bryant
KR
1991
Springer
15 years 9 months ago
Planning as Temporal Reasoning
This paper describes a reasoning system based on a temporal logic that can solve planning problems along the lines of traditional planning systems. Because it is cast as inference...
James F. Allen
AAAI
2008
15 years 8 months ago
Terminological Reasoning in SHIQ with Ordered Binary Decision Diagrams
We present a new algorithm for reasoning in the description logic SHIQ, which is the most prominent fragment of the Web Ontology Language OWL. The algorithm is based on ordered bi...
Sebastian Rudolph, Markus Krötzsch, Pascal Hi...
DLT
2004
15 years 7 months ago
Recognizable Sets of Graphs, Hypergraphs and Relational Structures: A Survey
New results on the recognizability of sets of finite graphs, hypergraphs and relational structures are presented. The general framework of this research which associates tightly a...
Bruno Courcelle
ERSA
2006
105views Hardware» more  ERSA 2006»
15 years 7 months ago
A Column Arrangement Algorithm for a Coarse-grained Reconfigurable Architecture
In a coarse-grained reconfigurable architecture, the functions of resources such as Arithmetic Logic Units (ALUs) can be reconfigured. Unlike the programmability of a general purp...
Yuanqing Guo, Cornelis Hoede, Gerard J. M. Smit